OSCAR 2023 Workshop - Program
Accepted Presentations:
-
Aman
Arora and Lizy John
Koios:
Open-Source Deep Learning Benchmarks for FPGA Research
-
Cheng
Tan, Nicolas Bohm Agostini, Ankur Limaye, Serena Curzel, Marco Minutoli, Vito
Giovanni Castellana, Joseph Manzano, Ang Li and Antonino Tumeo
SO(DA)^2:
Software Defined Architectures for Data Analytics
-
Javier
Campos, Zhen Dong, Javier Duarte, Amir Gholaminejad, Michael Mahoney, Jovan
Mitrevski and Nhan Tran
End-to-end
codesign of Hessian-aware quantized neural networks for FPGAs and ASICs
-
Kevin
Yunchuan Jiang, Joseph Zuckerman and Luca P. Carloni
Pipelining
an Open-Source Last-Level Cache
-
Zhigang
Wei, Aman Arora, Ruihao Li and Lizy John
ML4Accel:An
Open-Source Dataset for ML-Guided Accelerator Design
-
Giuseppe
Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker and Marian
Verhelst
HW-aware
mapping of Graph Neural Networks on RISC-V GPGPU: A Work-in-Progress
-
Jerry Zhao, Seah Kim, Borivoje
Nikolić, Krste Asanovic and Yakun Sophia Shao
An
Open-source Framework for Virtualized and Disaggregated RISC-V Accelerators
-
Allen Boston,
Roman Gauchi and Pierre-Emmanuel Gaillardon
Programming
Management Unit: Open-Source Core for Secure FPGA Bitstream Configuration
-
Yingjie Li, Alan Mishchenko
and Cunxi Yu
Verilog-to-PyG:
A Framework for Graph Learning and Argumentation on RTL Designs
-
Ang Li, Ting-Jung Chang, Fei
Gao and David Wentzlaff
Open-Source
FPGA on Silicon: Case Studies on PRGA, an Open-Source Framework for Building
& Programming Custom FPGAs
-
Yanwen
Xu, Ang Li and Tyler Sorensen
Evaluating
Shared Memory Heterogeneous Systems Using Traverse-compute Workloads
-
Yuto Nishida, Sahil Bhatia,
Shadaj Laddad, Hasan Genc, Sophia Shao and Alvin Cheung
Code
Transpilation for Hardware Accelerators
-
Nuzhat Yamin,
Dina Hussein and Ganapati Bhat
Towards
Open Source Platforms for Wearable Health Monitoring
-
Maximilian
Bremer, Nirmalendu Patra, Tan Nguyen, Cy Chan and Dilip Vasudevan
Accelerating
Open-Source Hardware Simulation Using Optimistic Parallel Discrete Event
Simulation
-
Khyati
Kiyawat, Sergiu Mosanu, Mircea Stan and Kevin Skadron
Open-Source
Processing-in-Memory Architecture Design through FPGA Emulation: A Case Study
Modeling Sieve
-
Kavya
Sreedhar, Mark Horowitz and Christopher Torng
A Fast
Open-Source Extended GCD Accelerator
Accepted Posters:
-
Andreas
Brokalakis, Alexandros Skyvalos, Konstantinos Georgopoulos and Sotirios
Ioannidis
Using
Dynamic Partial Reconfiguration to Secure Processors Against Cache
side-channel Attacks
-
Stefan Huemer,
Ahmad Sedigh Baroughi, Hadi Shahriar Shahhoseini and Nima Taherinejad
AxE: an
ApproXimate-Exact MPSoC platform
-
Konstantinos
Amplianitis, Athanasios Pegkos, Konstantinos Georgopoulos, Andreas
Brokalakis, George Christou and Sotiris Ioannidis
Introducing
HW-extended Containers to a RISC-V Soft Core Hosted on an FPGA
-
Luca Collini,
Joey Ah-Kiow, Christian Pilato, Ramesh Karri and Benjamin Tan
Identifying
Security Concerns in IP Designs Generated by High-Level Synthesis
-
Mircea Stan and Kevin Skadron
Twenty
Years Later - HotSpot at 20
-
Mattis Hasler
RoadRunner:
A modularized hardware design management and EDA tool runner
-
Yao Hsiao, Christopher
Fletcher and Caroline Trippel
Formal
Characterization of Hardware Transmitters
-
Saranyu Chattopadhyay,
Caroline Trippel, Clark Barrett and Subhasish Mitra
Generalized
QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators